Flip chip packages are formed by solder joints arranged in a grid pattern on one side of an integrated circuit or semiconductor die to conduct electrical signals between the semiconductor die and a substrate such as a printed circuit board (PCB) onto which it is mounted. Each solder joint comprises a pad with a bump of solder adhered to it, and these solder bumps are usually held in place with a tacky flux.
The semiconductor die is mounted onto a PCB substrate with conductive pads in a pattern that matches the grid pattern of the solder bumps. The assembly is then heated, typically in a reflow oven, to melt the solder bumps. Surface tension causes the molten solder to hold the package in alignment with the PCB at the correct separation distance while the solder cools and solidifies, forming soldered connections between the semiconductor die and the PCB.
A disadvantage of flip chip packages is that the solder bumps are not mechanically compliant like the leads of traditional lead frame packages. Therefore, bending due to differences in coefficient of thermal expansion between PCB substrates and semiconductor dice causes thermal stress, while flexing and vibration cause mechanical stress, which can cause the solder joints to fracture.
Such thermal or mechanical stress issues can be overcome by bonding the semiconductor die to the PCB substrate in a process called underfilling, in which an electrically-insulating adhesive such as an epoxy mixture is infused under the semiconductor die after it has been soldered to the PCB substrate. This effectively glues the semiconductor die to the PCB substrate. Moreover, the underfill is useful for reducing the effects of any thermal stress experienced by the solder joints by distributing the thermal expansion mismatch between the semiconductor die and the PCB substrate, preventing stress concentration in the solder joints which would lead to premature failure. An additional advantage of injecting underfill is that it limits tin whisker growth. There are several types of underfill materials in use with differing properties relative to workability and thermal transfer.
There are basically two approaches to post-assembly underfilling, namely capillary underfill (CUF) and molded underfill (MUF).
CUF is the most common approach used for volume production. In CUF, the underfill is dispensed by a needle or jet from one or two sides of the semiconductor die that has been bonded onto a PCB substrate. With the assistance of capillary action, the underfill completely fills the narrow space around the solder joints between the semiconductor die and the PCB substrate. The semiconductor die and the substrate are then firmly bonded by curing the underfill. However, since CUF is typically performed one semiconductor die at a time, low throughput is a major disadvantage.
For MUF, a modified epoxy molding compound (EMC) is used to mold the chip and to fill the space between the semiconductor die and the substrate. The encapsulant of the semiconductor die and the underfill are formed at the same time, which helps to increase the throughput using this process. However, there are various challenges to using MUF. For instance, the flow of MUF in-between the semiconductor dies and the substrate should preferably be assisted by vacuum to improve the reliability of the process. Next, the modified EMC should have silica fillers with very small sizes to ensure that it is of sufficiently low viscosity to fill the narrow space.
Furthermore, warpage of the package is a potential issue due to the material properties of EMC and the molding temperature is limited by the melting point of the solder joints. As a result, the standoff heights and pitches of the solder joints have to be relatively large to overcome the aforesaid disadvantages.